74LS164 register equivalent, 8-bit serial in/parallel out shift register.
s Gated (enable/disable) serial inputs s Fully buffered clock and serial inputs s Asynchronous clear s Typical clock frequency 36 MHz s Typical power dissipation 80 mW
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These 8-bit shift registers feature gated serial inputs and an asynchronous clear. A low logic level at either input inhibits entry of the new data, and resets the first flip-flop to the low level at the next clock pulse, thus providing complete cont.
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